Dennard scaling is no longer enough. “This one-dimensional version of the roadmap may not be sufficient anymore for the future,” said Van den hove (pictured) “we will have to tune our devices for specific applications.”
Future transistor architectures may include GAA devices built from a stack of nano sheets, den hove described severalincluding a gate-all-around device built up of a stack of nanosheets and the forksheet device in which the N and the P channel transistors are moved closer together and the CFET where N and P transistors are stacked on top Of eachother.
“This forksheet device, we see as an extension of the standard nano sheet concept, and we believe it will be introduced around the equivalent of the one nanometer generation,” said Van den hove.
“It’s clear that you can realize another very important step in cell size shrinking, but obviously at the expense of much more complex contacting schemes to contact the source and drain areas. But we believe that we have developed integration schemes that would enable such transistors by optimizing the epi processes, patterning processes, and leveraging very sophisticated deposition processes to enable the contacting structures,” said Van den hove.
Possible ways ahead are reducing the thickness of the silicon channels to reduce channel length by replacing the silicon with 2D materials — atomically flat mono layers — such as tungsten or molybdenum sulfides or selenides.
“We’ve recently demonstrated the first versions of devices fabricated using 300 millimeter equipment,” he said.
Acombination of continued dimensional scaling, new transistor architectures, new materials introduction, combined with innovative interconnect architectures (buried power rails) will be the secret to success.
“We believe that we can propose a roadmap for the next eight to 10 generations — with an introductory pace of two to two-and-a-half year cadence — would bring us a roadmap for the next 20 years,” said Van den hove.
Lithography remains key. “Just the lithography-based shrinking is getting harder,” said Van den hove, “it’s not stopping, but it’s getting harder and harder. The performance improvement that we are used to for single transistors from node to node has been slowing down. This is why we had to go to massive parallelisation.”
“The current version of EUV we believe will be extendable down to the two-nanometer generation or maybe even a node further, but to go beyond that, we will need a next version of EUV,” said Van den hove.
This will require bigger lenses and new system platforms to be developed. The optics must adhere to phenomenal specifications, 20 picometer accuracy over for a lens with a diameter of one meter.
“If we extrapolate this to the size of the earth, it means that we would have to polish the earth with an accuracy of the thickness of a human hair. This is unbelievable, mind boggling,” said Van den Hove. “We expect that the first machines will be ready next year.”
“We’re setting up, together with ASML, a joint high NA lab built around the first prototype machine, which will be interfaced to a TEL track and surrounded with the most advanced metrology capabilities,” continued Van den Hove, “we are doing that because the challenge to introduce high NA EUV in a timely fashion will be tremendous. It took us about 10 years to go from the first EUV scanner to insertion into high volume manufacturing. For high NA, we will have much less time, only three years. In order to derisk that introduction in manufacturing, we are setting up a very intensive program in order to develop all the key enabling building blocks, such as the mask technology and the materials using wet or dry UV resist, metrology and optics characterisation.”